Recently, devices for processing digital audio signals have been actively developed. This accompanies development of digital audio signal techniques used for connection between devices. A well-known example of such techniques is a data communication system (Document 1) in which: when audio data is transmitted by use of an infrared communication device (IrDA: Infrared Data Association), a 1-bit data sequence having been subjected to a PDM (Pulse Density Modulation) is transmitted.
FIG. 19 illustrates a structure of a data receiving apparatus which uses such infrared communication device.
As illustrated in FIG. 19, the data receiving apparatus includes a receiving section 1001, a speaker driving section 1002, and a speaker 1003. The data receiving apparatus causes the receiving section 1001 to receive a 1-bit data sequence having been subjected to a PDM and causes the speaker driving section 1002 to drive the speaker 1003. Examples of conventional means for receiving infrared ray, which is used in the receiving section 1001, include an IrDA receiving device and an infrared remote control receiving device. In consideration of a communication rate, an IrDA receiving device having 1.152 Mbps (MIR) or 4 Mbps (FIR) is appropriate for the infrared receiving means.
TABLE 1Specs of IrDA receiving deviceCommunication ratePulse widthT4 Mbps (FIR)(¼)*T500μ sec1.152 Mbps (MIR)(¼)*T868μ sec2.4 Kbps~115.2 Kbps(SIR)( 3/16)*T8.68μ sec~104μ sec
TABLE 2Specs of infrared remote control receiving deviceCommunicationratePulse widthT1 Kbps or lessDifferent withDifferent withrespect to eachrespect to eachtransmission codetransmission code
Further, the data receiving apparatus receives audio data having been converted into coarse-to-fine data of a pulse sequence by use of a PDM. Therefore, by including the receiving section 1001, the speaker driving section 1002, and the speaker 1003 which serves as an LPF, the data receiving apparatus can easily convert audio data into audio. In this way, the data receiving apparatus can be applicable to a wireless phone or other apparatuses by causing the infrared communication device to communicate audio data which is a 1-bit data sequence having been subjected to the PDM.
In reproducing audio from such 1-bit digital signal (PDM signal) or PWM signal, these modulation signals have small amplitudes and therefore a load (speaker) cannot be directly driven in response to the modulation signals. Therefore, in order to amplify the amplitudes of the modulation signals so that the load can be driven in response to the modulation signals, a class D amplifier is used in the speaker driving section 1002.
FIG. 20 illustrates a circuit structure of a switching amplifier stage in a conventional class D amplifier. FIG. 21 illustrates an operational waveform of the switching amplifier stage.
The class D amplifier which drives a speaker by use of a PDM signal or PWM signal includes the switching amplifier stage illustrated in FIG. 20. The switching amplifier stage includes: a high side switching element HSW provided at the side of a high potential power source; a low side switching element LSW provided at the side of a low potential power source (alternatively, ground); and transistors Q101 to Q104.
The high side switching element HSW and the low side switching element LSW are made of a power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) for example. Further, a high side gate driving circuit includes an inverter made of the transistor Q101 which is a pMOS transistor and the transistor Q102 which is an nMOS transistor. On the other hand, a low side gate driving circuit includes an inverter made of the transistor Q103 which is a pMOS transistor and the transistor Q104 which is an nMOS transistor.
As illustrated in FIG. 21, in the switching amplifier stage, when an input signal IN is Hi (“1”), a logic level of a high side gate GH (a gate of the high side switching element HSW) and a logic level of a low side gate GL (a gate of a low side switching element LSW) are Lo and an output signal out(p) is Hi. Further, in the switching amplifier stage, when the input signal IN is Lo (“0”), the logic level of the high side gate GH and the logic level of the low side gate GL are Hi and the output signal out(p) is Lo.
In the switching amplifier stage, when the high side switching element HSW and the low side switching element LSW are ON simultaneously, a shoot-through current flows between the high potential power source and the low potential power source via the switching elements HSW and LSW.
FIGS. 22(a) to 22(d) illustrate operations of two switching elements which constitute the last stage of a class D amplifier.
Here, the high side switching element HSW is a p channel MOSFET and the low side switching element LSW is an n channel MOSFET. When the logic level of the high side gate GH is “0”, the high side switching element HSW is ON. When the logic level of the high side gate GH is “1”, the high side switching element HSW is OFF. On the other hand, when the logic level of the low side gate GL is “1”, the low side switching element LSW is ON. When the logic level of the low side gate GL is “0”, the low side switching element LSW is OFF.
In a general operational condition, the high side switching element HSW and the low side switching element LSW operate in the manner illustrated in FIG. 22(c) or 22(d). In the operational condition illustrated in FIG. 22(c) (when an input signal IN is Hi), the switching element HSW is ON and the low side switching element LSW is OFF. Consequently, a driving current Id flows toward a load LD via the high side switching element HSW, which causes an output signal out(p) to be Hi. On the other hand, in the operational condition illustrated in FIG. 22(d) (when the input signal IN is Lo), the high side switching element HSW is OFF and the low side switching element LSW is ON. Consequently, the driving current Id flows from the load LD via the low side switching element LSW, which causes the output signal out(p) to be Lo.
As illustrated in FIG. 22(a), in a condition under which the high side switching element HSW and the low side switching element LSW which are connected with each other in series are ON, a shoot-through current Is flows via the high side switching element HSW and the low side switching element LSW. Contrary to the condition, as illustrated in FIG. 22(b), in a condition under which the high side switching element HSW and the low side switching element LSW are OFF, the shoot-through current Is does not flow.
Digital audio data is generally represented in a PCM (Pulse Code Modulation) format. In order to amplify the digital audio data by use of a class D amplifier, it is necessary to convert a PCM signal supplied from a medium such as a CD, an MD, and a DVD into a PDM signal for example (to perform a PDM conversion), by use of a special IC.
A data receiving apparatus which receives audio data as described above performs wireless communication and therefore is driven by use of a battery. A class D amplifier provided in the data receiving apparatus which is driven by use of a battery has such a problem that power consumption caused by the shoot-through current quickens consumption of a battery.
In order to solve the problem, there is adopted a driving method which makes an operational condition illustrated in FIG. 22(b), in which no shoot-through current flows. The operational condition in which the high side switching element HSW and the low side switching element LSW are OFF is generally referred to as a dead time. In a class D amplifier, in order to reduce a shoot-through current, there is generally provided a circuit for generating a dead time (see Document 2 for example).
FIG. 23 illustrates an example of a structure of a dead time generating circuit in a class D amplifier. FIG. 24 illustrates operations of the dead time generating circuit and a switching amplifier stage in the class D amplifier.
The dead time generating circuit illustrated in FIG. 23 includes an inverter 101, a delay circuit 102, an NOR circuit 103, and an NAND circuit 104.
In the dead time generating circuit, an input signal IN having been inverted by the inverter 101 is inputted to the NOR circuit 103 and the NAND circuit 104 as it is, whereas the input signal IN is delayed by the delay circuit 102 for a predetermined time and then is inputted to the NOR circuit 103 and the NAND circuit 104. Consequently, as illustrated in FIG. 24, the NOR circuit 103 outputs a logical NOR between an output of the inverter 101 (inverter output) and an output of the delay circuit 102 (delay output). Further, the NAND circuit 104 outputs a logical NAND between the inverter output and the delay output. Consequently, the logic level of the high side gate GH is Hi while the NOR output is Lo, so that the high side switching element HSW is OFF. On the other hand, the logic level of the low side gate GL is Hi while the NAND output is Lo, so that the low side switching element LSW is ON.
Here, the NOR output falls from Hi to Lo and after a delay time td0 given by the delay circuit 102, the NAND output falls from Hi to Lo. The NAND output rises from Lo to Hi and after the delay time td0, the NOR output rises from Lo to Hi. Consequently, during the delay time td0 from a time when the logic level of the high side gate GH changes to Hi to a time when the logic level of the low side gate GL changes to Hi, the high side switching element HSW and the low side switching element LSW are OFF. In the same way, during the delay time td0 from a time when the logic level of the low side gate GL changes to Lo to a time when the logic level of the high side gate GH changes to Lo, the high side switching element HSW and the low side switching element LSW are OFF. In this way, dead times dt1 and dt2 are obtained based on the delay time td0.
In the dead time generating circuit, a dead time is determined by use of a predetermined delay time given by the delay circuit, so that it is difficult to change the delay time. In order to avoid such inconvenience, Document 3 discloses an arrangement which allows prompt and easy adjustment of a dead time. This arrangement includes a dead time adjusting circuit for monitoring gate signals of a high side switching element HSW and a low side switching element LSW, generating, from the gate signal, a DC voltage signal which is proportional to a dead time, and adjusting the dead time on the basis of the DC voltage signal.
Document 1: Japanese Unexamined Patent Publication No. 135321/2004 (Tokukai 2004-135321; published on Apr. 30, 2004)
Document 2: Japanese Unexamined Patent Publication No. 170608/1982 (Tokukaisho 57-170608; published on Oct. 20, 1982)
Document 3: Japanese Unexamined Patent Publication No. 338715/2003 (Tokukai 2003-338715; published on Nov. 28, 2003)
A dead time may comparably vary with respect to each product. Therefore, the dead time adjusting circuit is adopted so that a dead time can be easily adjusted after a class D amplifier is produced (at a time of shipping the class D amplifier). However, the dead time adjusting circuit is not used after the class D amplifier is shipped as a product. Consequently, the dead time adjusting circuit merely complexes the structure of the class D amplifier, which prevents the class D amplifier to be produced in low costs.
On the other hand, if a dead time can be appropriately set in accordance with specs of a class D amplifier in designing the class D amplifier, then it is possible to almost omit the adjustment of a dead time.